The present invention generally relates to semiconductor memory devices and more specifically to the sensing of matchlines of a high-density Content Addressable Memory (CAM) system.
In general, a semiconductor memory circuit typically consists of an array of rows and columns. Each intersection of a row and column defines a memory xe2x80x9ccellxe2x80x9d that stores either a binary logic xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d.
There are many types of memory available for various storage applications. For retrieval processing of large amounts of data, an associative memory called Content Addressable Memory (CAM) is gaining widespread use in a variety of applications including data networking. The important feature of CAM is that it can perform a search and compare operation between specified user data and stored data and return match or mismatch results.
CAM arrays are also made up of intersections of rows and columns of CAM cells, as with most typical memories. In addition to rows and columns of cells, associated with each row of CAM cells is a matchline and a matchline detection circuit or sense amplifier that senses the changes in the logic state of a matchline for the cells in that row. The matchline sense amplifier detects a match or a mishmatch during a CAM search and compare operation. FIG. 4 illustrates a block diagram of a typical array of memory cells where the detection circuit DC is used to sense a match or mismatch on the matchline ML connected to a row of several CAM cells.
Conventionally, during matchline sensing, there is no reference level available to compare a matchline to be sensed, the selected matchline ML either remains at a precharged voltage (VDD, for example) for a match detection, or discharges (towards ground voltage VSS, for example) for a mismatch detection. A match or mismatch condition must be detected for each cell in a bit search operation, and every matchline ML must be sensed simultaneously with typically 32,000 other matchlines or more. Since matchlines typically discharge from the precharged voltage in the case of a mismatch in any bit, and statistically, mismatches are much more frequent than matches, dynamic power due to matchlines switching simultaneously becomes a significant factor in designing the CAM which has to be accounted for.
Moreover, in high-density memory systems where the number of CAM cells in each row can reach 128 or higher, the speed for discharging a matchline is virtually limited by the capacitance of the matchline. This inherent discharge limitation cannot cope with the fast switching speed of high-density CAM systems where the search cycle time is of the order of 15 ns.
A sensing scheme is therefore required that will limit the matchline voltage swing in order to reduce the dynamic power of sensing all the matchlines while allowing for high speed search operations under low power consumption.
There are several known approaches to designing match/mismatch detection circuits. FIG. 1 shows a prior art example for sensing a matchine as disclosed in U.S. Pat. No. 5,051,948 by Watabe et al. In this sensing scheme, a current-voltage conversion circuit is first used to convert the matchline current into a voltage value. This voltage is then sensed by a voltage sensing circuit using a dummy reference voltage. This design may not be suitable for high-density CAM systems for the following reasons:
a. the current to voltage conversion is performed by a CMOS inverter that is biased as an analog amplifier. Under this arrangement, DC power is constantly consumed during entire operation and such consumption of power would be well beyond the limits that a high-density integrated circuit package could handle;
b. The dummy reference voltage circuit also uses CMOS inverters as an analog amplifier. This scheme not only consumes DC power but also precludes the appropriate tracking of the reference voltage with that of the matchline under high-speed, high-density memory sensing conditions; and
c. The circuit blocks of this type of design consume a considerable amount of integrated circuit area.
In summary, the inhibiting characteristics of this prior art design, when applied to high-density CAM systems, are both power and area consumption.
FIG. 2 shows a second prior art circuit, as disclosed in U.S. Pat No. 5,012,448, utilized in a Read-only-Memory (ROM) multilevel memory. This sensing scheme incorporates two CMOS inverters that operate as small-signal amplifiers each connected to NMOS devices for current sensing. The sources of both the reference side NMOS and the matchline side NMOS are fed into a current mirror circuit. As in the first prior art discussed, this second prior art approach may not be suitable for high-density memory applications because of the unacceptably large dissipation of power. In addition, due to the current mirror arrangement, a full CMOS level swing cannot be efficiently achieved.
A third prior art design is disclosed in U.S. Pat. No. 4,763,026 for single-ended data sensing. As illustrated in FIG. 3, this approach generates a reference voltage from the dataline itself. However, a key disadvantage of this prior art approach is that the reference node VREF is allowed to float after being precharged. Based on the high capacitive load T14, the precharged voltage value of VREF is expected to remain at the same level during the sensing operation. The reliance on a high capacitive load to hold the precharged value of the reference node may not be appropriate because, in a VLSI interchip environment, high noise injections from high speed operations can corrupt the value of the capacitive load and cause an unintended reversal in operation. A second disadvantage of this prior art design is that such a large dummy capacitance requires an appreciably large area on the VLSI chip. This may be cumbersome and impractical for a high-density CAM arrangement where 32,000 or more matchline sense amplifiers are required.
In summary, there is clearly a need for matchline sense amplifiers that are capable of:
quickly sensing a (highly capacitive) matchline;
limiting the matchline swing; and
sense all matchlines simultaneously (32K and above),
but in a manner which reduces the portion of integrated chip area used for high-density memory applications and reduces heat dissipation.
The above identified disadvantages of the prior art are now overcome with a sensing amplifier circuit operating under low dynamic power.
It is an object of the present invention to provide a sensing amplifier circuit for detecting a change in an input signal at an input node under relatively low dynamic power while consuming relatively little integrated circuit area. In a specifically preferred embodiment the invention provides a sensing amplifier circuit for detecting a match or mismatch search condition on a high density content addressable memory matchline that is capable of:
rapidly sensing the capacitive matchline;
limiting the matchline voltage swing; and
sensing all matchlines simultaneously
providing the match and mismatch result for post processing under relatively low dynamic power while consuming little circuit area.
It is a further objective of the content addressable memory application of the present invention to provide a sensing amplifier circuit wherein a sense node to a differential amplifier is not allowed to float to an unknown voltage level during the sense phase in case of a match and is not affected by noise injection on the matchline from high-speed operation.
It is yet another objective of the content addressable memory application of the present invention to provide a sensing amplifier circuit wherein a reference node on the differential amplifier is:
allowed to self-track the matchline voltage level (including any variation thereof due to device mismatches or threshold changes) during the precharge phase and maintain this precharge level during the sense phase; and
not allowed to float after the precharge phase, thus ensuring that noise coupling does not corrupt the reference node during the sensing phase.
Therefore, in accordance with one aspect of the present invention, there is provided a detection circuit for detecting at an input node a change in an input signal comprised of four elements. The first element is a differential amplifier having a sense node and a reference node. The second element is a means for alternating the differential amplifier between a precharge phase and a sense phase. The third elements is a precharge means for providing an input signal precharge voltage to the input signal via an input device, said input device selectively coupling the sense node to the input signal upon a change in the input signal. The fourth element is a reference means for providing the reference node with a reference signal that continuously tracks the input precharge voltage during the precharge phase and actively maintains the input signal precharge voltage during the sense phase. These elements comprise an aspect of the invention wherein the detection circuit detects a change in the input signal during the sense phase by comparing signals on the sense and reference nodes.
In an embodiment of the invention a detection circuit as defined above, for detecting a match or mismatch search condition on a high density content addressable memory matchline wherein the input signal is derived from the matchline.
In accordance with another aspect of the invention, there is provided a method of detecting a change in an input signal comprised of five steps. The first step is to precharge he input signal to an input signal precharge level. The second step is to generate a reference signal that continuously tracks the input signal precharge level during a precharge phase, and actively maintaining the reference signal at the input signal precharge level during a sense phase. The third step is to derive a sense signal corresponding to the input signal during the sense phase. The fourth step is to compare the sense signal with the reference signal. The fifth step is to switch an output signal between a first state and a second state upon said change.
In accordance with another aspect of the invention, there is provided a precharge circuit for precharging a matchline within an array of CAM cells powered from first and second power supply terminals, having a predetermined first supply voltage at the first power supply terminal relative to the second power supply terminal, comprised of two elements. The first element is an input device positioned between the matchline and a sense node. The second element is a precharge device for coupling the sense node to the first power supply terminal during a precharge phase, wherein an state of the input device is reversed upon the matchline reaching a voltage lower than or equal to a pre-selected precharge voltage, and wherein the precharge voltage is lower than the first power supply voltage, all voltages being in absolute values relative to the second power supply terminal. In accordance with another aspect of the invention, there is provided a method of precharging a matchline during a precharge phase within an array of CAM cells comprised of two steps. The first step is to begin to precharge the matchline by coupling the matchline to a first power supply terminal via an input device. The second step is to decouple the matchline from the first power supply terminal, when the matchline reaches a pre-selected precharge voltage.
In accordance with another aspect of the invention, there is provided a detection circuit for detecting a match or mismatch search condition on a dynamic content addressable memory matchline comprised of three elements. The first element is a precharge means for precharging the matchline to a predetermined matchline precharge voltage during a precharge phase. The second element is a reference means for generating a reference voltage which tracks the matchline precharge voltage during the precharge phase and actively maintains the matchline precharge voltage during a sense phase. The third element is a differential amplifier for sensing a voltage difference between the reference voltage at a reference node and a sense node voltage at a sense node selectively coupled to the matchline via an input circuit during the sense phase.
In accordance with another aspect of the invention, there is provided a detection circuit for detecting a change on an input signal comprised of three elements. The first element is a precharge means for precharging the input signal to a pre-selected precharge voltage during a precharge phase. The second element is a reference means for generating a reference voltage on a reference node which tracks the precharge voltage during the precharge phase and actively maintains the precharge voltage level during a sense phase. The third element is a differential amplifier for sensing a voltage difference between the reference voltage and a sense node voltage coupled to the input signal.